Peking University has introduced a new 3D chip design platform aimed at supporting Huawei’s future semiconductor roadmap. The technology improves chip efficiency by optimizing three-dimensional architectures and reducing internal signal pathways. The project highlights China’s ongoing push to advance domestic chip capabilities amid continuing technology restrictions.
China’s Peking University has unveiled a new 3D chip design tool that could become a key component of Huawei’s semiconductor strategy. The software, developed in the electronic design automation (EDA) field, is designed to support Huawei’s LogicFolding architecture and advance next-generation chip development while reducing reliance on Western technologies.
According to researchers, the system enables engineers to design multilayer chip structures as a fully integrated three-dimensional architecture rather than stacking separately designed two-dimensional layers. Early testing reportedly showed a roughly 30% reduction in internal wiring length, improving performance, efficiency, and thermal management. The technology aligns with Huawei’s Tau Scaling Law approach, which focuses on reducing signal transmission delays inside chips rather than relying solely on transistor miniaturization.
The development comes as China continues to face U.S. export restrictions on advanced semiconductor equipment and chip-design technologies. Huawei has previously outlined ambitions to reach transistor densities comparable to 1.4-nanometer-class technologies by 2031, with future Kirin processors expected to incorporate LogicFolding-based designs. Analysts view the project as part of China’s broader effort to strengthen semiconductor self-sufficiency and build an independent technology ecosystem.